1. Field of the Invention
The present invention relates to a method for fabricating a split gate flash memory. In particular, the invention involves the formation of a memory cell for split gate flash memory.
2. Description of the Prior Art
Complementary metal oxide semiconductor (CMOS) memory is generally categorized into two groups: random access memory (RAM) and read only memory (ROM). RAM is a volatile memory, wherein the stored data disappears when power is off. On the contrary, turning off power does not affect the stored data in a ROM.
In the past few years, market share of ROM has been continuously expanding, and the type attracting the most attention has been flash memory. The fact that a single memory cell is electrically programmable and multiple memory cell blocks are electrically erasable allows flexible and convenient application that are superior to electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and programmable read only memory (PROM). Furthermore, fabricating flash memory is cost effective. Having the above advantages, flash memory has been widely applied in consumer electronic products, such as digital cameras, digital video cameras, mobile phones, notebooks, personal stereos and personal digital assistant (PDA).
Since portability of these electrical consumer products is strongly prioritized by consumers, the size of the products must be minimal. As a result, capacity of flash memory must increase, and functions must be maximized while sizes thereof are continuously minimized. Having an increased amount of access data, capacity of memory cells has been enhanced from 4 to 256 MB, and even 1 G byte will become the market trend in the near future. Masks are essential in conventional processes for fabricating flash memory, even for the most critical process of floating gate and control gate.
Conventional process for a split gate flash memory cell is further explained with references to FIGS. 1A-1F. In FIG. 1A, a p-type silicon substrate 100 is thermal oxidized by local oxidation (LOCOS) to form a field isolation region 105. An active area 107 is then formed by separating the field isolation region.
FIG. 1B is a cross-section of the line A-Axe2x80x2 in FIG. 1A, where a first insulating layer 110 is formed by silicon oxide on the surface of the substrate 100 within the active area 107. Then, a polysilicon layer is formed by chemical vapor deposition (CVD) on the first insulating layer 110, followed by doping a suitable amount of dopant to form a first conductive layer 115. Silicon nitride is then deposited on the surface of the first conductive layer 115 to form a first masking layer 120 as a hard mask.
In FIG. 1C, part of the first masking layer 120 is removed to define a first opening 125 and expose the surface of the first conductive layer 115.
Next, oxidation is performed to form a floating gate oxide layer 130 on the exposed first conductive layer 115, as shown in FIG. 1D.
Then, in FIG. 1E, the first masking layer 120 is removed by isotropic etching, followed by using the floating gate oxide layer 130 as a hard mask to perform anisotropic etching. In this step, part of the first conductive layer 115 and the first isolating layer 110 are sequentially removed. The first conductive layer 115 and the first insulating layer 110 located underneath the floating gate oxide layer 130 remain, while the surface of substrate 100 is exposed. The remaining first conductive layer 115 becomes a floating gate 136, and the remaining first insulating layer 110 becomes a first gate insulating layer 112. Conductive tip 138, formed when forming the floating gate 136, discharges the floating gate 136 when data is being erased in the flash memory. Next, oxidation or CVD is performed to form a second insulating layer 132 using silicon oxide, to cover the substrate 100, surface of the floating gate oxide layer 130, and sidewalls of the floating gate 136 and the first gate insulating layer 112.
A second conductive layer 135 is then formed by doped polysilicon, to cover the surface of the second insulating layer 132, as shown in FIG. 1F.
Then, in FIG. 1G, photolithography and etching are performed to remove part of the second conductive layer 135 and the second insulating layer 132 to form a second opening 142 and a third opening 144. The remaining second conductive layer 135 becomes a control gate 170, and the remaining second insulating layer 132 becomes the second gate insulating layer 155.
In FIG. 1H, N-type dopant, such as Phosphorous ions or Arsenic ions are doped into the substrate 100 to form a source region 180 within the second opening 142 in the substrate 100. Next, an oxide layer (not shown) is then deposited to cover the surface and sidewalls of the control gate 170, sidewalls of the second gate insulating layer 155, surface of the floating gate oxide layer 130, the floating gate 136 and sidewalls of the first gate insulating layer 112. Etching is then performed to remove part of the oxide layer to form insulating sidewall layers 150 on the sidewalls of the second opening 142 and the third opening 144. Then, N-type dopant, such as Phosphorous ions or Arsenic ions are doped into the substrate 100 to form a drain region 190 within the third opening 144 in the substrate 100. This completes the conventional process for fabricating a split gate flash memory cell.
Conventionally, a floating gate oxide layer is firstly formed on the conductive layer of doped polysilicon. Next, anisotropic etching is performed to remove the conductive layer of doped polysilicon not covered by the floating gate oxide layer. Hence, the conductive layer of doped polysilicon underneath the floating gate oxide forms the floating gate. However, sizes of all elements must be decreased when integration of memory cell rapidly increases. Due to the fact that the floating gate insulating layer is formed by oxidation in conventional processes, accuracy cannot meet the requirements of highly-integrated memory cells.
In order to overcome the above problems, major features of the invention are as follows:
(1) Floating gate and floating gate insulating layer are formed by self-alignment: a conductive layer and an insulating layer are firstly formed on a substrate, followed by simultaneously forming a shallow trench isolation (STI) and defining the insulating layer in the active area to form a first gate insulating layer (commonly referred as floating gate insulating layer). A conductive sidewall layer is then formed on the first gate insulating layer, followed by using the first gate insulating layer and the conductive sidewall layer as a hard masks to remove the conductive layer not covered by the hard mask. A floating gate is then formed by the conductive sidewall layer and the conductive layer underneath. Since the floating gate is formed by self-alignment, size and process are easy to control without influence of line width. In addition, floating gate can be accurately formed in the active area in the shallow trench isolation (STI). However, misalignment frequently occurs in conventional process when forming a floating gate in the shallow isolation trench (STI). Consequently, a floating gate is not formed in the predetermined accurate position in the active area, and gaps are formed between floating gate and shallow trench isolation. It can be even more serious at later stages when implanting ions to form source/drain regions, where leakage path occurs in the gaps between floating gate and the shallow trench isolation. As a result, data stored in the floating gate disappears, thus the function of flash memory is lost. The floating gate cannot be programmed nor erased. Besides, it cannot gate the channel.
(2) Anisotropic etching is used to form the conductive sidewall layer to ensure the formation of a more shaped conductive tip than is conventionally made and an easier controlled process.
(3) Floating gate and shallow trench isolation (STI) are simultaneously formed by simpler process.
According to the key points listed above, a method for fabricating a split gate flash memory cell is provided in this invention, comprising the following steps: providing a substrate; forming an oxide layer on the substrate; forming a first conductive layer on the oxide layer; forming a first insulating layer on the first conductive layer; forming a second insulating layer on the first insulating layer; forming a first opening by removing part of the second insulating layer, the first insulating layer, the first conductive layer, oxide layer and substrate, thereby defining the position of the field isolation region, wherein an active area is located between neighboring field isolation regions; forming a third insulating layer to cover the remaining second insulating layer and extending into the first opening to cover the sidewalls and bottom of the first opening; forming a fourth insulating layer to cover the third insulating layer and fill the first opening; removing sequentially the remaining fourth insulating layer and third insulating layer on the surface of the second insulating layer, only keeping the part within the first opening; leaving part of the remaining fourth insulating layer in the first opening to form a second opening, wherein the remaining fourth insulating layer is shallow trench isolation; forming a fifth insulating layer to fill the second opening; defining a gate region by photolithography and etching, followed by removing the remaining second insulating layer and first insulating layer outside the gate region to expose the surface of the remaining first conductive layer, wherein the remaining first insulating layer in the gate region is the first gate insulating layer, and part of the third insulating layer and fifth insulating layer are removed simultaneously when removing the second insulating layer in this step, the removed thickness is the same as that of the second insulating layer; forming a second conductive layer to cover the sidewalls of the first gate insulating layer, surface and sidewalls of the second insulating layer in the gate region and the surfaces of the first conductive layer and the fifth insulating layer, and the surface and sidewalls of the third insulating layer outside the gate region; removing the first conductive layer, surface of the fifth insulating layer, and surface and sidewalls of the third insulating layer not covering the gate region, part of second conductive layer covering the surface and sidewalls of the remaining second isolating layer inside the gate region, to form a conductive sidewall layer on the sidewall of the first gate insulating layer, which is the tip of polysilicon; using the remaining second insulating layer, first gate insulating layer and the conductive tip as a hard mask to remove the first conductive layer and oxide layer not covered by the remaining second insulating layer, first gate insulating layer and conductive tip, and the remaining first conductive layer and conductive tip are combined to form a floating gate, and the remaining oxide is a gate oxide layer; removing the remaining fifth insulating layer, second insulating layer and part of the remaining third insulating layer to expose the surface of the shallow trench isolating and the first gate insulating layers; forming a sixth insulating layer to cover the substrate and surface of the shallow trench isolation, surface and sidewalls of the third insulating layer, the gate oxide layer, the floating gate, sidewalls of the conductive tip and upper surface of the first gate insulating layer; forming a third conductive layer to cover the surface of the sixth insulating layer; sequentially removing part of the third conductive layer and the sixth insulating layer to form a third opening and a fourth opening, and the remaining third conductive layer forms a control gate and the remaining sixth insulating layer form a second gate insulating layer; forming a source region on the substrate within the third opening; forming a insulating sidewall layer on the sidewalls of the third opening and the fourth opening; and forming a drain region on the substrate within the fourth opening.